The method for forming a target etch profile according to the present invention has special applicability to the formation of container cells for semiconductor capacitors but is not limited thereto. Capacitors in the form of container cells are used in a wide variety of semiconductor circuits. Capacitors are of special importance in DRAM (dynamic random access memory) memory circuits; therefore, the invention will be particularly discussed in connection with DRAM memory circuits. However, the invention has broader applicability and is not limited to DRAM memory circuits. It may be used in other types of memory circuits, such as SRAMs, as well as any other integrated circuit in which capacitors are used, or in which maximizing the volume of etched cells within a given cell area is desired, or in which there is a need for a semiconductor via or other cavity having a target etch profile.
Known container capacitors are in the shape of an upstanding tube (cylinder) with an oval or circular cross section. The wall of the tube consists of two plates of conductive material such as doped polycrystalline silicon (referred to herein as polysilicon or poly) separated by a dielectric. The bottom end of the tube is closed, with the outer wall in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open. The sidewall and closed end of the tube form a container; hence the name "container capacitor."
FIG. 2 illustrates a step in the formation of a container capacitor in which the container cell area 144 is prepared for the deposition and etching of an Interlevel Dielectric Material (IDM). Following the deposition and etching of the IDM layer, a conductive layer is then deposited within the container cell. The surface area of this conductive material determines the capacitance of the capacitor and is dependent on the volume of the container cell. The volume of the container cell in turn is dependent upon the successful etching of the IDM layer.
In constructing a container cell, the IDM layer is typically composed of borophosphosilicate glass (BPSG); phosphosilicate glass (PSG), silicon dioxide, or the like. When the etchant is applied, the amount of etching performed is dependent upon the etch rate and the length of time the etchant is applied. The direction of the etch is determined by the degree to which the selected etching process is isotropic or anisotropic. Etching which proceeds in all directions at the same rate is said to be "isotropic". By definition, any etching that is not isotropic is anisotropic. Wet etching, for example, is isotropic. Many etching processes typically fall between the extremes of being isotropic and completely anisotropic and, therefore, some unwanted etching is common even under the best conditions of prior etching processes.
Ideally, the process used to etch the IDM layer would be completely anisotropic, as this would produce a completely vertical container wall. However, as the etching of the IDM layer occurs at least somewhat isotropically, some unwanted etching in the horizontal direction occurs. In other words, as etching processes are applied for a length of time to etch in a downward direction for a required depth, etching also occurs in an outward direction. This typically causes a widening or bowing out at the top of the etched container cell. The isotropic component of the etch process is a function of the etch conditions, the etch rate, and the characteristics of the material being etched.
As illustrated in FIG. 1a, the resulting shape of the container cell is one in which the sidewalls 150 are sloped and hence the volume of the container is not maximized. This results in less room for conductive material and lower capacitance for the container capacitor. FIG. 1b illustrates an ideal container cell in which the side walls 152 are vertical and hence the container volume is maximized.
FIG. 1c illustrates an overlapping comparison of the sloping wall 150 container versus the straight wall 152 container. The lost volume 160 caused by the sloping of the walls decreases the surface area of the container capacitor and thus the capacitance of the resulting capacitor.
As memory cell density continues to increase, efficient use of space becomes ever more important. Therefore, what is needed is an etching process and container capacitor that make more efficient use of available memory cell space.
Further, as the trend of scaling down and the need for fabricating extremely precise submicron components continue, it is becoming increasingly important to provide techniques for fabricating substantially straight vertical sidewalls and various other precise target etch profiles.